16 STAGE PIPELINE Search Results

Contextual Info: High Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate AD9260 STAGE 1:2X 16-BIT: DECIMATION 10MHz FILTER REFERENCE BUFFER DRVDD DRVSS DIGITAL DEMODULATOR 12-BIT: 20MHz AD9260 STAGE 2:2X 16-BIT: DECIMATION 5MHz FILTER OTR 16-BIT: STAGE 3:2X

diode T35 12H

Abstract: 100NS PQFP144 ST10F167 ST10F167 Controller disassembler st10 Bootstrap
Contextual Info: ST10F167 16-BIT MCU WITH 128KBYTE FLASH MEMORY • HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE. – 16-BIT CPU WITH 4 STAGE PIPELINE – 100NS INSTRUCTION CYCLE TIME AT 20MHz CPU CLOCK – 500NS MULTIPLICATION 16*16 BIT – 1µS DIVISION (32/16 BIT)

74HC245 application

Abstract: ad780r 100k trimpot pin configuration 1K variable resistor pin configuration transistor 2N2222 AD9260-EB PIN CONFIGURATION 2N2222 AD9260 ttl buffer 74hc245 star delta ladder diagram
Contextual Info: High Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate AD9260 STAGE 1:2X 16-BIT: DECIMATION 10MHz FILTER REFERENCE BUFFER DRVDD DRVSS DIGITAL DEMODULATOR 12-BIT: 20MHz AD9260 STAGE 2:2X 16-BIT: DECIMATION 5MHz FILTER OTR 16-BIT: STAGE 3:2X

L29C520

Abstract: LPR520 LPR520JC25 LPR520PC15 LPR520PC22 LPR520PC25 y10 smd
Contextual Info: LPR520 LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register

L29C520

Abstract: LPR520 LPR520JC15 LPR520JC22
Contextual Info: LPR520 LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register

LPR520

Abstract: LPR520JC22 L29C520
Contextual Info: LPR520 LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register

Contextual Info: LPR520/521 LPR520/521 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline

Contextual Info: LPR520 □ FV IC E S IN C O R P Q R A T F D FEATURES 4 x 16-bit Multilevel Pipeline Register DESCRIPTION □ Four 16-bit Registers □ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register The LPR520 is functionally compat­ ible with the L29C520 but have 16-bit

L1823

Abstract: DI437 smd diode Y5
Contextual Info: L Q G / C L P R 5 2 0 4 x 16-bit Multilevel Pipeline Register DRVICES INCORPORATED FEATURES_j □ Four 16-bit Registers □ Im plem ents Double 2-Stage Pipe­ line or Single 4-Stage Pipeline •Register □ H old, Shift, and Load Instructions

Contextual Info: 4 x 16-bit Multilevel FEATURES □ Four 16-bit Registers □ Implements Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ Hold, Shift, Load Instructions □ Separate Data In and Data Out Pins □ High Speed, Low Power CMOS Technology □ Three-State Outputs

Contextual Info: LPR520 D E V IC E S IN C O R P O R A T E D FEATURES 4 x 16-bit Multilevel Pipeline Register DESCRIPTION □ Four 16-bit Registers □ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register The L P R 520 is functionally compat­ ible with the L29C520 but have 16-bit

Contextual Info: LPR520/521 4 x 16-bit Multilevel Pipeline Register V IC I S INCORPORA ILL DESCRIPTION FEATURES □ Four 16-bit Registers □ Implements Double 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ Hold, Shift, and Load Instructions □ Separate Data In and Data Out Pins

Contextual Info: LPR520/521 4 x 16-bit Multilevel Pipeline Register DESCRIPTION FEATURES □ Four 16-bit R egisters □ Im plem ents D ouble 2-Stage Pipe­ line or Single 4-Stage Pipeline Register □ H old, Shift, and L oad Instructions □ Separate D ata In an d D ata O ut Pins

CFB2430A

Contextual Info: CFB2430A CFB2430A MPY •1PL GENERAL D ESC R IPTIO N : 16 X 12 MIXED-MODE MPY, 1-STAGE PIPELINE The CFB2430A megafunction is a 16 X 12 mixed mode, 1-stage pipeline MPY. Sign interpretation o f the inputs is controlled by TCX and TCYN: The multiplicand is unsigned if TCX is LOW, and two’s comple­

Contextual Info: ST10F167 16-bit MCU with 128KByte FLASH memory DATASHEET High Performance CPU • 16-bit CPU with 4 stage pipeline • 100ns instruction cycle time at 20MHz CPU clock • 500ns multiplication 16*16 bit • 1(as division (32/16 bit) • Enhanced boolean bit manipulation

SUSCON capacitor

Abstract: ST10F168-Q3 transmitter circuit in GPR st10f168s SUSCON PQFP144 ST10F168 diode T35 12H st10 Bootstrap
Contextual Info: ST10F168 16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE – 80ns INSTRUCTION CYCLE TIME AT 25MHz CPU CLOCK – 400ns 16 X 16-BIT MULTIPLICATION – 800ns 32 / 16-BIT DIVISION – ENHANCED BOOLEAN BIT MANIPULATION

Contextual Info: SCS-THOMSON *JM > DSll g|g@ilUl inMID @ ST10R163 16-BIT ROMLESS MICROCONTROLLER DATASHEET High performance 16-bit CPU with 4-stage pipeline 80ns instruction cycle time at 25-MHz CPU clock 400 ns multiplication (16 x 16 bits , 800 ns division (32 /1 6 bit)

Contextual Info: CFB2402A CFB2402A MPY - 1PL GENERAL DESCRIPTION: 16 X 16 TWO’S COMP PLAIN MPY, 1-STAGE PIPELINE, CS CFB2402A is a 16 x 16 two’s complement multiplier that takes two 16-bit numbers and multiplies them together to form a 32-bit number. Four clockjnputs CPI - CP4 and four enable_inputs (EN1 - EN4)

Contextual Info: SGS-THOMSON ST10R 165 iM ig ia o iiU K g T r M n 16-BIT ROMLESS MICROCONTROLLER PRELIMINARY DATA High performance 16-bit CPU with 4-stage pipeline 100 nsinstruction cycle timeat20-MHz CPU clock 500 ns multiplication 16 x 16 bits , 1 jos division (32/16 bit)

API3

Contextual Info: CFB2401B CFB2401B MPY - 1PL GENERAL DESCRIPTION: 16 X 16 TWO’S COMP PLAIN MPY, 1-STAGE PIPELINE CFB2401B is a 16 x 16 two’s complement multiplier that takes two 16-bit numbers and multiplies them together to form a 32-bit number. There is only one clock input CP to control the pipelining function.

Contextual Info: LPR520 4 x 16-bit Multilevel Pipeline Register FEATURES DESCRIPTION □ Four 16-bit Registers The LPR520 is functionally compatible with the L29C520 but have 16-bit inputs and outputs. The LPR520 is implemented in low power CMOS. □ Implements Double 2-Stage Pipe­

Contextual Info: Æ 7 SGS-THOMSON •>71. llD giœi!J iMraD(g§ ST10F167 16-BIT MCU WITH 128K BYTE FLASH MEMORY PRELIMINARY DATA • High PerformanceCPU ■ 16-bit CPU with 4 stage pipeline. ■ 100 ns instruction cycle time at 20MHz CPU Clock. ■ 500ns multiplication (16*16 bit ,

Contextual Info: / IT G S-1 H 0 M S0 N #. SIMOtg^lULKgìfMnigg_ ST10R163 16-BIT ROMLESS MICROCONTROLLER D ATASH EET • High performance 16-bit CPU with 4-stage pipeline ■ 80ns instruction cycle time at 25-MHz CPU clock ■ 400 ns multiplication 16 x 16 bits , 800 ns

T71N

Abstract: LT17 t71c ST10 ST10F167 017FFE st10 Bootstrap TS cc30, thomson
Contextual Info: SGS-THOMSON su ST10F167 16-BIT MCU W ITH 128K BYTE FLASH M EM O RY P R E L IM IN A R Y DA TA High PerformanceCPU 16-bit CPU with 4 stage pipeline. 100 ns instruction cycle time a t20M H z CPU Clock. 500ns multiplication 16*16 bit , 1 ms division (32/16 bit).