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    9015DM/B Rochester Electronics LLC 9015 - QUAD NOR Gate Visit Rochester Electronics LLC Buy
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    Rochester Electronics LLC 9015DM-B

    9015DM/B
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    Microchip Technology Inc MCP2515DM-BM

    EVAL BOARD FOR MCP2515 MCP2551
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    Teledyne e2v QP7C198L-15DMB

    STATIC RAM, 32K X 8, LOW-POWER, 15 NS AC - Rail/Tube (Alt: QP7C198L-15DMB)
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    Teledyne e2v QP7C198-15DMB

    STATIC RAM, 32K X 8, 15 NS ACCESS TIME - Rail/Tube (Alt: QP7C198-15DMB)
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    Teledyne e2v CY7C464A-15DMB

    FIFO MEMORY, 32K X 9, 15 NS ACCESS TIME - Rail/Tube (Alt: CY7C464A-15DMB)
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    15DMB Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    AT3864L-15DMB

    Abstract: AT3864L-15DM power-40mA
    Text: AT3864L-15DMB Features • • • • • • • • • • Fast Read Access Time -15 0 ns Low Power 40 mA Maximum Active 1 mA Maximum (Standby) 2-V Data Retention Fully Static: No Clock Required _ Three Control Inputs (CEi, CE2 , and OE) TTL Compatible Inputs and Outputs


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    AT3864L-15 28-Lead AT3864L-15DMB 1D7M177 AT3864L-15DMB AT3864L-15DM power-40mA PDF

    Untitled

    Abstract: No abstract text available
    Text: AT3864L-15DMB Features • • • • • • • • • • Fast Read Access Time -150 ns Low Power 40 mA Maximum Active 1 mA Maximum (Standby) 2-V Data Retention _ Fully Static: No Clock Required Three Control Inputs (CEi, CE2 , and OE) TTL Compatible Inputs and Outputs


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    AT3864L-15DMB 28-Lead AT3864L-15DMB Its64K 00Q53Rb> PDF

    Untitled

    Abstract: No abstract text available
    Text: AT3864L-15DMB Features • • • • • • • • • • Fast Read Access T im e-150 ns Low Power 40 mA Maximum Active 1 mA Maximum (Standby) 2-V Data Retention Fully Static: No Clock Required _ Three Control Inputs (C E i, CE 2, and OE) TTL Compatible Inputs and Outputs


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    AT3864L-15DMB e-150 28-Lead AT3864L-15DMB AT3864L- 15DMB PDF

    Untitled

    Abstract: No abstract text available
    Text: AT3864L-15DMB Features • • • • • • • • • • Fast Read Access Time •150 ns Low Power 40 mA Maximum Active 1 mA Maximum (Standby) 2-V Data Retention Fully Static: No Clock Required _ Three Control Inputs (CEi.CEz, and OE) TTL Compatible Inputs and Outputs


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    AT3864L-15DMB 28-Lead AT3864L-15DMB PDF

    Untitled

    Abstract: No abstract text available
    Text: AT3864L-15DMB Features • • • • • • • • • • Fast Read Access Time - 1 50ns Low Power 40mA Maximum Active 1mA Maximum (Standby) 2V Data Retention Fully Static: No Clock Required _ Three Control Inputs (CE 1 , CE 2, and OE) TTL Compatible Inputs and Outputs


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    AT3864L-15DMB AT3864L-I5DMB AT3864L-15DMB 150ns 220mW PDF

    CY7C187

    Abstract: CY7C187A
    Text: CY7C187A 64K x 1 Static RAM Features provided by an active LOW chip enable CE and three-state drivers. The CY7C187A has an automatic power-down feature, reducing the power consumption by 55% when deselected. • High speed — 20 ns • CMOS for optimum speed/power


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    CY7C187A CY7C187A CY7C187 PDF

    C1507

    Abstract: C1504 C1502 c1509 C150 CY7C150 R1329
    Text: CY7C150 1Kx4 Static RAM Features Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable OE is held HIGH, allowing for


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    CY7C150 C1507 C1504 C1502 c1509 C150 CY7C150 R1329 PDF

    C401 diode

    Abstract: 10DC IR transistor 10dc ir C4016 C4019 C401 CY7C401 CY7C402 CY7C403 C4013
    Text: CY7C401/CY7C403 CY7C402/CY7C404 64 x 4 Cascadable FIFO 64 x 5 Cascadable FIFO Features words. Both the CY7C403 and CY7C404 have an output enable OE function. • 64 x 4 (CY7C401 and CY7C403) 64 x 5 (CY7C402 and CY7C404) High-speed first-in first-out memory (FIFO)


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    CY7C401/CY7C403 CY7C402/CY7C404 CY7C403 CY7C404 CY7C401 CY7C403) CY7C402 CY7C404) 25-MHz 50-ns C401 diode 10DC IR transistor 10dc ir C4016 C4019 C401 C4013 PDF

    CY7C197

    Abstract: No abstract text available
    Text: CY7C197 256Kx1 Static RAM Features vided by an active LOW chip enable CE and three-state drivers. The CY7C197 has an automatic power-down feature, reducing the power consumption by 75% when deselected. • High speed — 12 ns Writing to the device is accomplished when the chip enable


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    CY7C197 256Kx1 CY7C197 PDF

    7cl6

    Abstract: D-2501 CY7C161A CY7C162 CY7C162A
    Text: CYPRESS SEMICONDUCTOR 4bE » B SSfl'lbfe.S □ QQbMSb b q c y p CY7C161A CY7C162A • - j/ "— = 16,384 x 4 Static RAV RAM Separate I/O SEMICONDUCTOR Features • Automatic power-down when dese­ lected • Transparent write 7C161A • CMOS for optimum speed/power


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    CY7C161A CY7C162A 7C161A) CY7C162 au62A-35DMB CY7C162Aâ 35KMB CY7C162A-35LMB CY7C162A-45DMB 7cl6 D-2501 CY7C162A PDF

    TP 152N

    Abstract: CI23 k7315 2A mosfet igbt driver stage as256words CY7C123
    Text: MbE D CYPRESS SEMICONDUCTOR E3 2 S 0 ciL.iJ2 D D O b B I R 7 C l C Y P CY7C123 CYPRESS SEMICONDUCTOR Functional Description 256 x 4 static RAM for control store in high-speed computers CMOS foroptimum speed/power High speed — 7 ns commercial — 10 ns (military)


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    QQQta31R CY7C123 300-mil CY7C123 as256words CY7C123-12LC CY7C123â 12DMB 12LMB TP 152N CI23 k7315 2A mosfet igbt driver stage PDF

    K73 Package

    Abstract: 3 phase inverter schematic diagram 7C166 CY7C164A CY7C166A CI64A CY7C164A-45DMB
    Text: 4bE D CYPRESS SEM IC ON DU CT OR □ - p q & eSÛ'IbbE OQObMfiS 2 R3CYP .r S - l O C Y 7 C I6 4 A C Y 7 C 1 6 6 A ";ui'./^CTPRESS , _ SEMICONDUCTOR 16,384 x 4 Static R/W RAM Features Functional Description • Automatic power-down when


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    CY7C164A CY7C166A 384x4 CY7C166A 35DMB CY7C166Aâ 35KMB CY7C166A-35LMB K73 Package 3 phase inverter schematic diagram 7C166 CI64A CY7C164A-45DMB PDF

    7C192-12

    Abstract: 7C192-15 7C192-20 A10C CY7C191 CY7C192 CY7C192-25PC
    Text: MbE D CYPRESS SEMICON DUC TOR B 250^fc,b2 OOQfc.1,42 3 E 3 C Y P CY7C191 CY7C192 CYPRESS SEMICONDUCTOR Features • Automatic power-down when deselected • Transparent write 7C19X • CMOS for optimum speed/power • H ighspeed — tM = 25 ns • Low active power


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    CY7C191 CY7C192 7C19X) TheCY7C191 CY7C192 CY7C192-45VC CY7C192-45DMB CY7C192-45KMB CY7C192â 45LMB 7C192-12 7C192-15 7C192-20 A10C CY7C192-25PC PDF

    CY7C101A

    Abstract: CY7C102A 7C101A-12 l3lx
    Text: PRELIMINARY 9 / C Y PR E SS CY7C101A CY7C102A 256K x 4 Static RAM with Separate I/O Features Functional Description • High speed The CY7C101A and CY7C102A are high­ perform ance CMOS static RAM s orga­ nized as 262,144 x 4 bits with separate I/O. Easy m emory expansion is p rovided by ac­


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    CY7C101A CY7C102A 7C101A) CY7C102A CY7C101A tdwel161 7C101A 8-00231-A 7C101A-12 l3lx PDF

    AB26S

    Abstract: 7C109A CY7C109 CY7C109A
    Text: CY7C109A PRELIMINARY l ^wSSQBBSf S S ySSt Ì p YJe JkP XRI- XjiïJF ^ 128KX 8 Static RAM Features Functional Description • H ighspeed The CY7C109A is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable


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    CY7C109A 128Kx CY7C109A AB26S 7C109A CY7C109 PDF

    CY7C197

    Abstract: CV7C197
    Text: MbE D n " T CYPRESS SEMICONDUCTOR Features Automatic power-down when deselected CMOS for optimum speed/power Highspeed — 20ns Low active power — 880 mW Low standlgr power — 220 mW TlX-compatible imputs and outputs Capable ofwithstanding greater than


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    CY7C197 2001Velectrostatic CY7C197 CY7C197-45LC CY7C197-45PC CY7C197-45VC CY7C197-45DMB CY7C197-45KMB CY7C197-45LMB CV7C197 PDF

    CY7C1009

    Abstract: 7C1009 A14C
    Text: PRELIMINARY r y f|pPA RJL- lrP Anni I CY7C1009 128Kx 8 Static RAM Features Functional Description • Highspeed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 1020 mW • Low standby power — 250 mW The CY7C1009 is a high-performance


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    CY7C1009 550-mil CY7C1009 7C1009 A14C PDF

    P4C148

    Abstract: P4C149
    Text: P4C148, P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Two Options – P4C148 Low Power Standby Mode – P4C149 Fast Chip Select Control High Speed Equal Access and Cycle Times – 10/12/15/20/25/35/45/55 ns (Commercial) – 15/20/25/35/45/55 ns (P4C148 Military)


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    P4C148, P4C149 P4C148 P4C149 096-bit PDF

    P4C150

    Abstract: No abstract text available
    Text: P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM FEATURES Separate Input and Output Ports Full CMOS, 6T Cell Three-State Outputs High Speed Equal Access and Cycle Times – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Fully TTL Compatible Inputs and Outputs


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    P4C150 24-Pin 28-Pin P4C150 096-bit requires300 SRAM105 PDF

    P4C147

    Abstract: No abstract text available
    Text: P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell Single 5V ± 10% Power Supply High Speed Equal Access and Cycle Times – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Separate Input and Output Ports Three-State Outputs


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    P4C147 SRAM103 SRAM103 P4C147 Oct-05 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C106A PRELIMINARY y CYPRESS 256K x 4 Static RAM Features Functional D escription • High speed T he CY7C106A is a high-perform ance CM O S static R A M organized as 262,144 words by 4 bits. Easy m em ory expansion is provided by an active LO W chip enable


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    CY7C106A CY7C106A PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7B194 CY7B195 CY7B196 PRELIMINARY CYPRESS SEMICONDUCTOR 65,536 x 4 Static R/W RAM Features Functional Description • High speed — tAA = 10 ns • BiCMOS for optimum speed/power • Low active power — 825 mW • Low standby power — 330 mW • Automatic power-down when


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    CY7B194 CY7B195 CY7B196 CY7B195 CY7B196 CY7B194, 7B195, PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C408A CY7C409A " s CYPRESS SEMICONDUCTOR Features • 64 x 8 and 64 x 9 first-in first-out FIFO buffer memory • 35-MHz shift in and shift out rates • Almost Full/Almost Empty and Half Full flags • Dual-port RAM architecture • Fast (50-ns) bubble-through


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    CY7C408A CY7C409A 35-MHz 50-ns) CY7C408A) 300-mil, 28-pin PDF

    Untitled

    Abstract: No abstract text available
    Text: PAL22V10C _ PAL22VP10C Universal PAL Device SEMICONDUCTOR Features • • Ultra high speed supports today’s and tomorrow’s fastest microprocessors 10 user>programmable output macrocells — Output polarity control — Registered or combinatorial


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    PAL22V10C PAL22VP10C PAL22VP10C) 28-Pin PAL22VP10CM 28-Square PAL22VP10CM 15KMB 12YMB PDF