1284H Search Results

Contextual Info: MT9M002: 1/4.5-Inch 1.6Mp CMOS Digital Image Sensor Features 1/4.5-Inch 1.6Mp CMOS Digital Image Sensor MT9M002 For the latest MT9M002 data sheet, refer to Aptina’s Web site: www.aptina.com Features Table 1: • DigitalClarity CMOS imaging technology • Maximum frame rate 1284H x 812V/60 fps at 99

Contextual Info: Features Datasheet RX64M Group Renesas MCUs R01DS0173EJ0100 Rev.1.00 Jul 31, 2014 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, full-speed USB 2.0 with battery charging, SD host interface optional , quad SPI, and CAN, 12-bit A/D

Contextual Info: Datasheet RX62T Group Renesas MCUs R01DS0096EJ0100 Rev.1.00 Apr 20, 2011 100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC 3 S/H circuits, double data register, amplifier, comparator : two units, 10-bit ADC one unit, the three ADC units are capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary

R01US0032EJ

Contextual Info: User’s Manual 32 Cover RX63T Group User’s Manual: Hardware RENESAS 32-Bit MCU RX Family / RX600 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by

1037h

Abstract: 1250H 1488h MX12 MX23 PM5365
Contextual Info: PM5365 TEMAP STANDARD PRODUCT DATASHEET PMC-1991148 ISSUE 3 HIGH DENSITY VT/TU MAPPER AND M13 MULTIPLEXER PM5365 TEMAP VT/TU MAPPER AND M13 MULTIPLEXER DATA SHEET PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 3: SEPTEMBER 2001 Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use

1250H

Abstract: 1000H 1006H 100CH 100DH
Contextual Info: ACPI Implementation for the i960 RM/RN I/O Processor Application Note August 1999 Order Number: 273255-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

TLCS-90

Abstract: BC001 tlcs90 HL008 HL123 40p03 TLCS-900 a55H tlcs-90 cpu xor 1237h
Contextual Info: TLCS-900/L1 CPU 900, 900/L, 900/H, 900/L1, 900/H2 CPUコアの違いについて TLCS-900ファミリにはCPUコアとして① 900, ② 900/L, ③ 900/H, ④ 900/L1, ⑤ 900/H2の5種の CPUコアがあり、それぞれ表1に示す点が異なります。

Contextual Info: PM8315 TEMUX STANDARD PRODUCT DATASHEET ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX :5 4: 01 AM PMC-1981125 co n Fr id ay ,2 TEMUX 9O ct ob er ,2 00 4 10 PM8315 DATASHEET PROPRIETARY AND CONFIDENTIAL ISSUE 7: MAY 2001 Do wn lo

HTR resistors

Abstract: 80960 80960SA reference i960 RP Processor 80960JF STT 433 1250H clock generator in dual core processor i960 Cx Instruction Set Quick Reference i960 Cx Processor Instruction Set Quick Reference
Contextual Info: i960 RP Microprocessor User’s Manual i960® RP Microprocessor User’s Manual February 1996 Order Number: 272736-001 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for

80960

Abstract: BO 620 bbc timer stt 11 c17f i960 Cx Processor Instruction Set Quick Reference i960RP 80960JF 80960RD 80960RP MA11
Contextual Info: i960 Rx I/O Microprocessor Developer’s Manual Release Date: April, 1997 Order Number: 272736-002 The i960® Rx I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Such errata are

TP-128

Contextual Info: Features DATASHEET RX63T Group Renesas MCUs R01DS0087EJ0200 Rev.2.00 Mar 11, 2013 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, Two 12-bit ADCs three S/H circuits, double data registers, amplifier, comparator , one 10-bit ADC, simultaneous sampling on 7 channels using three ADCs, 100 MHz PWM (2 three-phase complementary channels + 4 single-phase

MT9M032

Abstract: 5 MP Auto-Focus Camera with LED Flash cmos IMAGE SENSOR global shutter MT9M032C12STC MT9M032C12STMU CMOS digital image sensor with global shutter CMOS image sensor with global shutter high speed CMOS global shutter KIT MT9M032 MT9M032C12STMUES
Contextual Info: Advance‡ MT9M032: 1/4.5-Inch 1.6Mp CMOS Digital Image Sensor Features 1/4.5-Inch 1.6Mp CMOS Digital Image Sensor MT9M032 For the latest data sheet, refer to Micron’s Web site: www.micron.com/imaging Features Table 2: • DigitalClarity CMOS imaging technology

R5F563T6EGFM

Contextual Info: Features DATASHEET RX63T Group Renesas MCUs R01DS0087EJ0210 Rev.2.10 Sep 26, 2013 100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, Two 12-bit ADCs three S/H circuits, double data registers, amplifier, comparator , one 10-bit ADC, simultaneous sampling on 7 channels using three ADCs, 100 MHz PWM (2 three-phase complementary channels + 4 single-phase

bt 1488

Abstract: ST2101 1182h HA 1156 R OSC CMOS CLOCK 32.768K pc 2561 thermister 247 simple Thermister circuit DD 127 D TRANSISTOR OSC CMOS 32.768K
Contextual Info: ST ST2100 8 BIT MICROCONTROLLER WITH 2M BYTES ROM Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change. 1. FEATURES Totally static 8-bit CPU

1587H

Contextual Info: PM8315 TEMUX PRELIMINARY DATASHEET PMC-981125 ISSUE 4 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MULTIPLEXER DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY

0B-09

Abstract: bip 109
Contextual Info: PM5365 TEMAP PRELIMINARY DATASHEET PMC-991148 ISSUE 1 VT/TU MAPPER AND M13 MUX PM5365 TEMAP VT/TU MAPPER AND M13 MULTIPLEXER DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 1: SEPTEMBER 1999 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

63A52

Abstract: PM5360 Hex schmitt trigger ecl isp connector block diagram 0521H 10A1H 0836H 1E6C
Contextual Info: 22 AM S/UNI MULTI-48 ASSP Telecom Standard Product Data Sheet Released be r, 20 04 07 :2 3: PM5360 y, 14 Se pt em S/UNI® MULTI-48 in er In co n Tu es da Multi-rate SATURN® User Network Interface for 1x2488, 4x622, and 4x155 Released Issue No. 5: September 2003

stepper motor interface with 8086 block diagram

Abstract: pcd4541 PCL6045A G9004 pcl6045 PCL6045B DP101-102F G9001 8031 intel LD11
Contextual Info: Motionnet G9004 CPU emulation device User's Manual Nippon Pulse Motor Co., Ltd. [Preface] Thank you for considering our super high-speed serial communicator LSI, the "G9000." To learn how to use the G9000 series device, read this manual and "G9001/G9002" user's manual

TLCS-90

Abstract: 8001H PS42A tlcs-900 TMP93CS32 tlcs90 tlcs-90 cpu xor TMP95 bcd cc 106 1p0
Contextual Info: TLCS-900/L CPU 900, 900/L, 900/H, 900/L1, 900/H2 CPU Core Different Points There are 5 type CPU core: ① 900, ② 900/L, ③ 900/H, ④ 900/L1, ⑤ 900/H2 in TLCS-900 Family and they are different from following points. CPU 900 900/L 900/H, 900/L1 Address Bus

tmp96c141

Abstract: PC 1278H 2001H TLCS-900
Contextual Info: T O S H IB A TLCS-900 JP condition, dst < Jum p > Operation : If cc is true, then PC < - dst. Description : If the operand condition is true, jumps to the program address specified by dst. Details F lags Mnemonic : S S Z H V N C JP #16 JP #24 JP [cc,] mem

PC 1278H

Abstract: 123AH 00123457H
Contextual Info: TO SH IB A TLCS-900/H CPU HALT < H alt CPU > Operation : CPU halt Description : H alts the instruction execution. To resume, an interrupt m ust de received. Details : Mnemonic HALT Flags : S S Z H V N C Z H V N = = = = = = Code 0|0|0|0|0|1|0|1 C No change

a8293

Abstract: A8294 A8264 PC 1498H 1250H a8296 BA RV cb rv 1050H REQ64
Contextual Info: Intel 80312 I/O Companion Chip Developer’s Manual December 2000 Order Number: 273410-002 Intel® 80312 I/O Companion Chip Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual

LB 124 d

Abstract: BH RV transistor i960 Cx Processor Instruction Set Quick Reference 80960JT 80960RM 80960RN REQ64 BIT3102 273160 80960
Contextual Info: i960 RM/RN I/O Processor Developer’s Manual July 1998 Order Number: 273158-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

GC80960RS100

Abstract: p16c182 P16C180V GC80960RN100 I960R 1250H capacitor 106c intel schematics 80960RM 80960RN
Contextual Info: Intel i960® RM/RN/RS I/O Processor Specification Update September 4, 2001 Notice: The 80960RM/RN/RS processor may contain design defects or errors known as errata. Characterized errata that may cause the product’s behavior to deviate from pubished specifications are documented in this specification update.