02FEB2004 Search Results

M950x0

Abstract: EEPROM F6SP36 6512 AI123
Contextual Info: M950x0 M950x0-W M950x0-R 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface Positive clock SPI modes ■ Single supply voltage: – 4.5 V to 5.5 V for M950x0 – 2.5 V to 5.5 V for M950x0-W

Contextual Info: Preliminary Data Sheet Part Number 856305 298.74 MHz SAW Filter Features • • • • • • • • For GPS IF applications Usable bandwidth of 2.0 MHz Low loss High attenuation Balanced operation Ceramic Surface Mount Package SMP Small size Also available in a 5.0 x 5.0 mm package

M50FLW080

Abstract: M50FLW080A M50FLW080B PLCC32 TSOP32
Contextual Info: M50FLW080A M50FLW080B 8 Mbit 13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors 3V Supply Firmware Hub / Low Pin Count Flash Memory FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ FLASH MEMORY – Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1)

Contextual Info: M950x0 M950x0-W M950x0-R 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface Positive clock SPI modes ■ Single supply voltage: – 4.5 V to 5.5 V for M950x0 – 2.5 V to 5.5 V for M950x0-W

Contextual Info: 2 THIS C DRAWING IS UNPUBLISHED. C O P Y R I G H T 20 BY - RELEASED ALL FOR PUBLICATION RIGHTS 20 LOC RESERVED. DIST REVISIONS 00 GP LTR DESCRIPTION REVISED El PADS LIGHT PIPE I7 6 I0 I2 - I 2\ KIT AND V IA S DATUM AND C H A S S IS BASIC PER DATE E C O - 1 1- 0 0 7 0 5 2

Contextual Info: 4 TH IS DRAWING IS U N P U B L IS H E D . COPYRIGHT RELEASED BY 17C 0 2 3 ELECTRONICS CORPORATION. FOR PUBLIC ATIO N ALL RIGHTS R E V IS IO N S R E S ER V ED . AF 50 P LTR H D E S C R IP TIO N R E V IS E D PER DATE DWN 06MAY08 E C R - 0 8 - 0 1 1 1 12 APVD

Contextual Info: 4 3 THIS DRAWING IS UNPUBLISHED. COPYRIGHT RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. _ i_ LOC DIST AF 50 ALL RIGHTS RESERVED. REVISIONS LTR DESCRIPTION REVISED PER 0 G 3 A - 0 0 5 5 - 0 4 CONTINUOUS D STRIP 1 0 .8 m m 2 [# 18 ] (1) 1 .3 m m 2

Contextual Info: M950x0-W M950x0-R 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock Datasheet - production data Features • Compatible with SPI bus serial interface Positive clock SPI modes • Single supply voltage: – 2.5 V to 5.5 V for M950x0-W

Contextual Info: TH I S DRAW ING IS UNPUBLI SHED. COPYRI GHT 2 0 0 2 R EL E AS E D FOR PUBL I CATI ON BY TYCO E L E CT RONI CS CORPORATI ON. AL L RI GHTS 200 2 LOC .8 - m ROW A ROW B — E= s- 2.5 p LTR D E S C R 1PTI ON DATE DWN APVD R E L E A S E D PER EC OS 1 2 - 0 0 5 2 - 0 2

Contextual Info: 2 TH I S DRAW ING IS U NP UBL I S HE D. R E L E A S E D FOR P U B L I C A T I O N BY TYCO E L E C T R O N I C S C O P Y R I G H T 20 CORPORATION. ALL RIGHTS 20 LOC AD RE S E RV E D. 1\ A R E V 1S I O N S D I ST 00 p PHOSPHOR BRONZE LCP, UL94V-0 LTR D E S C R 1P T I O N

FB600

Abstract: M50FLW080 M50FLW080A M50FLW080B PLCC32 TSOP32
Contextual Info: M50FLW080A M50FLW080B 8 Mbit 13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors 3V Supply Firmware Hub / Low Pin Count Flash Memory PRODUCT PREVIEW FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ FLASH MEMORY – Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1)

Contextual Info: THIS DRAWING IS UNPUBLISHED. C O P Y RI G HT 2 0 0 3 BY RELEASED TYCO ELECTRONICS CORPORATION. ALL FOR PUBLICATION R|3 H T $ ’ 00 3 LOC AD RESERVED. REV I S I O N S D I ST 00 LTR Al THRU ROW HG GROUND ROW H ROW G ROW RG (GROUND) ROW R ROW E (GROUND) RO W D

M95010

Abstract: M95010-R M95010-W M95020 M95020-R M95020-W M95040 M95040-R M95040-W
Contextual Info: M95040 M95020 M95010 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface Positive clock SPI modes ■ Single supply voltage: – 4.5 V to 5.5 V for M950x0 – 2.5 V to 5.5 V for M950x0-W

AI12304

Abstract: M950x0 ufdfpn8 M95010 M95010-R M95010-W M95020 M95020-R M95020-W M95040
Contextual Info: M95040 M95020 M95010 4 Kbit, 2 Kbit and 1 Kbit Serial SPI bus EEPROM with high speed Clock Feature summary • Compatible with SPI bus serial interface Positive Clock SPI Modes ■ Single supply voltage: – 4.5 V to 5.5 V for M950x0 – 2.5 V to 5.5 V for M950x0-W

95040W6

Abstract: 95040w
Contextual Info: M95040 M95020, M95010 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ Compatible with SPI Bus Serial Interface Positive Clock SPI Modes Single Supply Voltage: – 4.5 to 5.5V for M950x0

Contextual Info: 2 TH I S DRAW ING IS U NP UBL I S HE D. C O P Y R I G H T 20 BY TYCO E L E C T R O N I C S R E L E A S E D FOR P U B L I C A T I O N CORPORATION. ALL RIGHTS LOC R E V 1S I O N S D I ST AD RE S E RV E D. 00 p PHOSPHOR BRONZE LCP, UL94V-0 LTR D E S C R 1P T I O N

FB02002

Abstract: FB130
Contextual Info: M50FLW080A M50FLW080B 8 Mbit 13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors 3V Supply Firmware Hub / Low Pin Count Flash Memory PRODUCT PREVIEW FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ FLASH MEMORY – Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1)

ufdfpn8

Abstract: M95010 M95010-R M95010-W M95020 M95020-R M95020-W M95040 M95040-R M95040-W
Contextual Info: M95040 M95020 M95010 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock Features • Compatible with SPI bus serial interface Positive clock SPI modes ■ Single supply voltage: – 4.5 V to 5.5 V for M950x0 – 2.5 V to 5.5 V for M950x0-W

M50FLW080A

Abstract: M50FLW080 M50FLW080B PLCC32 TSOP32
Contextual Info: M50FLW080A M50FLW080B 8-Mbit 13 x 64-Kbyte Blocks + 3 x 16 × 4 Kbyte Sectors 3-V supply, Firmware Hub / low-pin-count Flash memory Feature summary • ■ ■ ■ ■ ■ Flash memory – Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1) used

Contextual Info: M50FLW040A M50FLW040B 4 Mbit 5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors 3V Supply Firmware Hub / Low Pin Count Flash Memory FEATURES SUMMARY • FLASH MEMORY Figure 1. Packages – ■ Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1)

sh 94v-0

Contextual Info: 2 TH I S DRAW ING IS U NP UBL I S HE D. R E L E A S E D FOR P U B L I C A T I O N BY TYCO E L E C T R O N I C S COPYRIGHT 2 0 0 3 CORPORATION. ALL RIGHTS 2003 LOC REV 1S I O N S D I ST 00 AD RE S E RV E D. p LTR D E S C R 1P T I O N DATE DWN APVD R E L E A S E D PER OS 1 2 - 0 2 5 3 - 0 3

Contextual Info: 2 TH I S DRAW ING IS U NP UBL I S HE D. COPYRIGHT 2 0 0 2 BY TYCO E L E C T R O N I C S R E L E A S E D FOR P U B L I C A T I O N CORPORATION. ALL RIGHTS 200 2 LOC REV 1S I O N S D I ST 00 AD RE S E RV E D. p LTR D E S C R 1P T I O N DATE DWN APVD R E L E A S E D PER EC OS 1 2 - 0 0 5 2 - 0 2

Contextual Info: £L TH I S DRAW ING IS U NP UBL I S HE D. COPYRIGHT 2 0 0 2 200 2 R E L E A S E D FOR P U B L I C A T I O N BY TYCO E L E C T R O N I C S CORPORATION. ALL RIGHTS LOC RE S E RV E D. AD REV 1SIONS D I ST 00 p A B B1 - o I mu ] ] — E H s- 2 . 5 RE F n m it