0031FC Search Results

Contextual Info: Philips Semiconductors tb53^31 0031b73 3=n APX Product specification NPN 4 GHz wideband transistor — — BFQ136 N AUER PHILIPS/DISCRETE b^E ]> PINNING DESCRIPTION NPN transistor in a four-lead dual-emitter SOT122A envelope with a ceramic cap. Ail leads are isolated

Contextual Info: MB91550 Series 32-bit Microcontroller FR Family FR81S MB91F552 Data Sheet Full Production Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume

82C206

Contextual Info: 47E D SIEMENS • flaasbos 0031S7D 1 « S I E G SIEMENS AKTIE NGE SELLSCHAF -rs a -3 S -5 5 SAB 82C211 CPU/Bus Controller of Siemens PC-AT Chipset Advance Information 117 3.90 47E » ■ Ö 535b05 0031571 SIEMENS AKTIENGESELLSCHAF -•

Contextual Info: PRELIMINARY BiCMOS SRAM KM616BV4002 25 6K x 16 Bit High-Speed BiCMOS Static RAM 3.3V Operating FEATURES GENERAL DESCRIPTION • Fast Access Time 12,15,20 ns(Max.) • Low Power Dissipation Standby (TTL) : 60 mA(Max.) (CMOS):30 mA(Max.) Operating KM 616BV4002J-12 : 240m A (M ax.)

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Abstract: DAC600 DAC600AN DAC600BN 33.8Mhz
Contextual Info: Or, Call Customer Service at 1-800-548-6132 USA Only B U R R - BROWN « E DAC600 1 DEMO BOARD AVAILABLE See Appendix A o o CD O < 12-Bit 256MHz Monolithic DIGITAL-TO-ANALOG CONVERTER Û (f) FEATURES • • • • • cc APPLICATIONS 12-BIT RESOLUTION 256MHz UPDATE RATE

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Contextual Info: HB56D836BR/SBR Series, HB56D436BR/SBR Series 8,388,608-Word x 36-Bit High-Density Dynamic RAM Module 4,194,304-Word x 36-Bit High-Density Dynamic RAM Module HITACHI ADE-203-729A Z Rev. 1.0 Feb. 20, 1997 Description The HB56D836BR/SBR is an 8 Mbit x 36 dynamic RAM module, mounted in 16 pieces of 16-Mbit

M-25012 states

Abstract: CY7C1360V25 CY7C1362V25 CY7C1364V25
Contextual Info: ^ „ CY7C1360V25 CY7C1362V25 W ^ T Y P R F .S S PREUm NARY CY7C 1364V25 256K X 36/256K x 32/512K x 18 Pipelined SRAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max­