DSAAQ0016219.pdf by Cypress Semiconductor

Partial File Text CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Late
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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3M Touch Systems