DSARS004977.pdf by Cypress Semiconductor

Partial File Text CY7C1346F 2-Mbit (64K x 36) Pipelined Sync SRAM Functional Description[1] Features · Registered inputs and outputs for pipelined operation · 64K × 36 common I/O architecture · 3.3V core powe
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CY7C1346F CY7C1346F-100AC CY7C1346F-133AC CY7C1346F-166AC