DASF0047607.pdf by Renesas Technology

Partial File Text Renesas LSIs M5M5V5636GP 16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM DESCRIPTION The M5M5V5636GP is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is d
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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M5M5T5636GP M5M5V5636GP M5M5V5636GP-13 M5M5V5636GP-16

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