This site uses third-party website tracking technologies to provide and continually improve our services, and to display advertisements according to users' interests. I agree and may revoke or change my consent at any time with effect for the future.
HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No.
History
0.1
Defined Preliminary Specification
0.2
1)
2)
3)
4)
5)
6)
0.
