DSAAQ0026731.pdf by Silicon Laboratories

Partial File Text CY2SSTV855 Differential Clock Buffer/Driver Features · Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications · 1:5 differential outputs · External feedback p
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CY2SSTV855ZI CY2SSTV855ZI CY2SSTV855ZCT CY2SSTV855ZIT CY2SSTV855ZXCT

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