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DSAAQ0026731.pdf
by Silicon Laboratories
Partial File Text
CY2SSTV855 Differential Clock Buffer/Driver Features · Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications · 1:5 differential outputs · External feedback p
Datasheet Type
Original
RoHS
No
Pb Free
No
Lifecycle
Obsolete
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