DSA0052220.pdf by QuickLogic

Partial File Text QAN1 Registers and Latches in the pASIC Architecture INTRODUCTION Quicklogic's pASICTM 1 Family of high-performance FPGAs allows logic function speeds of over 100 MHz. The prime objective of t
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"7400 series" 7400 application notes 7400 family 7400 J-K Flip-Flop 7400 series 7400 series logic gates 74104 74104 shift register 74105 74171 74174 shift register 74194 74194 design and application shift register 74194 introduction 74194 latch 74194 shift register 74194 shift register internal 74273 74273 latch application note 74273 multiplexer 74278 74373 74373 register 74374 74374 74373 74374 register 74376 74395 74594 74604 7474 D latch 7474 flip-flop 7474 for shift register 7474 shift register 7477 D latch 7478 J-K Flip-Flop 7478 jk 74822 74841 7491 16-bit 7491 8-bit 7491 shift register 7498 4 bit 7498 register feedback multiplexer latch 74373 latch 74374 Latches 74373 ql8x12 QL8X12B Register 74373 schematic design multiplexer shift register 7491 shift register by using D flip-flop 7474 which logic family is 7474