DSA00218616.pdf by Xilinx

Partial File Text Application Note: Spartan-6 FPGAs Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) XAPP1064 (v1.0) December 23, 2009 Author: NIck Sawyer Summary Spartan®-6 devices
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"parameters S" BUFIO2 Clock-Generator clock_generator_ddr_s8_diff IDELAY iodelay ISERDES ISERDES spartan 6 ISERDES2 OSERDES oserdes2 oserdes2 DDR spartan6 serdes SP601 testbench of a oserdes2 in verilog X10640 XAPP1064