DSASW0010763.pdf by PMC-Sierra

Partial File Text RM7000B Preliminary 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 125 MHz max. freq., multiplexed address/data bus (SysAD) · Supports two outstanding reads with out-of-ord
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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64120A EV-64120A-7000 GT-64120A IEEE754 RM7000 RM7000B

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