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Partial File Text fS] I nc 3.3V Low Skew CMOS PLL Clock Driver With Integrated Loop Fi Iter QS5LV919 FEATURES/BENEFITS JEDEC compatible LVTTL level Clock inputs are 5V tolerant < 300ps output skew, Q0-Q4 2xQ
Datasheet Type Scan
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown

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