DSAE0031141.pdf by Xilinx

Partial File Text Application Note: Virtex-5 Family Virtex-5 FPGA Interface to a JESD204A Compliant ADC XAPP876 (v1.0) September 18, 2009 Author: Marc Defossez Summary This application note describes how
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adc controller vhdl code DS202 JESD204 JESD204A ML505 picoblaze UG347 VHDL code for ADC and DAC SPI with FPGA VHDL code for ADC and DAC SPI with FPGA spartan 3 VHDL code for high speed ADCs using SPI with FPGA vhdl code for parallel to serial converter vhdl code for transceiver using UART vhdl program for parallel to serial converter XAPP876 xilinx 8 pin dip package outlines