The recommended power-up sequence is to apply VDD first, followed by VDDA, and then the digital interface signals (e.g., I2C, SPI). This ensures that the analog and digital sections of the device are properly initialized.
To configure the WM8768 for master clock mode, set the MCLK pin as an output by writing to the Clock Control Register (address 0x04). Then, set the desired clock frequency using the Clock Frequency Register (address 0x05).
The maximum allowed capacitance on the VDDA pin is 10uF. Exceeding this value may affect the device's power-up behavior and analog performance.
To optimize the WM8768's analog performance, ensure that the device is properly decoupled, and the analog and digital grounds are separated. Additionally, adjust the analog output stage's gain and impedance to match your specific application's requirements.
Keep analog and digital signals separate, and use a star-ground configuration to minimize noise and crosstalk. Route analog signals away from digital signals, and use shielding or guard rings to protect sensitive analog nodes.
