The recommended power-up sequence is to apply VDD first, followed by VDDA, and then the digital interface signals (e.g., I2C, SPI). This ensures that the analog and digital sections of the device are properly initialized.
To configure the WM8768 for master clock mode, set the MCLK pin as an output by writing to the Clock Control Register (0x04). Then, set the desired clock frequency using the Master Clock Frequency Register (0x05).
The maximum allowed capacitance on the VREF pin is 10nF. Exceeding this value may affect the device's performance and stability.
To optimize the WM8768's performance for low-power operation, reduce the clock frequency, disable unused features, and adjust the power-down modes for the analog and digital sections. Refer to the Power Management section in the datasheet for more details.
Keep analog and digital signals separate, use a solid ground plane, and minimize trace lengths and loops. Place decoupling capacitors close to the device's power pins, and use a common mode filter (e.g., ferrite bead) on the analog input signals.
