The recommended power-up sequence is to apply analog power (AVDD) first, followed by digital power (DVDD), and then bring the reset pin (RST) high.
To configure the WM8737 for master clock mode, set the MCLK pin as an output by setting the MCLKOE bit in the Clock Control Register (0x04). Then, set the desired clock frequency using the MCLKDIV bits in the Clock Control Register.
The Zero-Cross Detector (ZCD) pin is used to detect the zero-crossing point of the analog input signal, allowing for synchronized sampling and reducing distortion.
To optimize the ADC performance, ensure that the analog input signal is within the recommended range (typically 2.2Vpp), and adjust the ADC gain settings using the ADC Gain Control Register (0x10). Additionally, ensure proper grounding and decoupling of the analog power supply.
The maximum allowed capacitance on the analog input pins is 10nF. Exceeding this value may affect the ADC's performance and accuracy.
