The recommended power-up sequence is to apply analog power (AVDD) first, followed by digital power (DVDD), and then bring the reset pin (RST) high.
To configure the WM8737 for master clock mode, set the MCLK pin as the clock source, and set the MCLKDIV pin to select the desired clock frequency. Additionally, set the BCLK pin to output the bit clock, and the LRCLK pin to output the left-right clock.
The maximum input level for the ADC is 2.5Vrms, which corresponds to a maximum signal amplitude of 3.5Vpp.
To optimize the WM8737 for low power consumption, use the power-down modes (PDN and PDN_ADC) to disable unused blocks, reduce the clock frequency, and adjust the analog power supply voltage (AVDD) to the minimum required for the application.
The recommended layout and routing for the WM8737 involves separating analog and digital signals, using a solid ground plane, and minimizing signal trace lengths and vias. Additionally, use a decoupling capacitor (e.g., 10uF) between AVDD and AGND, and a decoupling capacitor (e.g., 10uF) between DVDD and DGND.
