A 4-layer PCB with a dedicated ground plane and careful routing of analog and digital signals is recommended. Refer to the Cirrus Logic application note AN215 for more details.
Use the device's power-down modes, reduce the clock frequency, and optimize the analog circuitry to minimize power consumption. Refer to the datasheet section 8.2 for more details.
A high-quality, low-jitter clock source such as a crystal oscillator or a high-precision clock generator is recommended. The clock frequency should be 12.288 MHz or 24.576 MHz for optimal performance.
Check the ADC clock frequency, analog input signal amplitude, and PCB layout for noise and interference. Use the device's built-in diagnostic features, such as the ADC test mode, to help identify issues.
Use a digital filter, such as a finite impulse response (FIR) filter, to filter the digital output and reduce noise and aliasing. The decimation ratio should be chosen based on the specific application requirements.
