The recommended power-on sequence is to apply power to the DVDD and CVDD pins first, followed by the AVDD and DVDDIO pins. This ensures that the internal voltage regulators are powered up correctly.
The clock domains on the DM368 can be configured using the Clock Domain Control Registers (CDCR). The CDCR registers allow you to select the clock source, clock frequency, and clock mode for each domain.
The maximum frequency of the ARM926EJ-S core on the DM368 is 432 MHz. However, the actual operating frequency may be lower depending on the specific application and power consumption requirements.
The VPSS on the DM368 can be used to accelerate video processing tasks such as video encoding, decoding, and scaling. The VPSS is configured using the VPSS registers and can be controlled using the ARM926EJ-S core.
The DM368 has a 16-bit external memory interface that can address up to 64 MB of external memory. However, the actual amount of external memory that can be connected depends on the specific application and memory configuration.
TMS320DM368ZCED48F datasheet
by Texas Instruments
