TMS320DM368ZCE48 datasheet by Texas Instruments

TMS320DM368ZCE48 Frequently Asked Questions (FAQs)

• What is the recommended power-on sequence for the DM368?
  The recommended power-on sequence is to apply power to the DVDD and CVDD pins simultaneously, followed by the AVDD and DVDDIO pins. This ensures proper power-up of the device.
• How do I configure the clock settings for the DM368?
  The clock settings can be configured using the Clock Enable Register (CKEN) and the Clock Divider Register (CKDIV). The CKEN register enables or disables the clock for each module, while the CKDIV register sets the clock divider ratio.
• What is the maximum frequency of the ARM926EJ-S core?
  The maximum frequency of the ARM926EJ-S core is 432 MHz. However, the actual operating frequency may be lower depending on the system design and clock configuration.
• How do I use the Video Processing Subsystem (VPSS) on the DM368?
  The VPSS can be configured using the VPSS registers and the Video Input/Output (VIO) module. The VPSS supports various video interfaces, including ITU-R BT.656, ITU-R BT.1120, and HDMI. Refer to the VPSS user guide for detailed configuration and programming information.
• What is the purpose of the External Memory Interface (EMIF) on the DM368?
  The EMIF provides an interface to external memory devices, such as SDRAM, DDR2, and asynchronous SRAM. It allows the DM368 to access external memory for storing and retrieving data.