The recommended power-on sequence is to power up the core voltage (VDD_CORE) first, followed by the I/O voltage (VDD_IO). This ensures that the internal voltage regulators are properly enabled.
The DM365 uses a PLL-based clocking system. The clock source can be configured using the PLL controller registers. The clock frequency can be set using the PLL multiplier and divider registers.
The maximum operating frequency of the DM365 is 720 MHz. However, the actual operating frequency may vary depending on the specific application and operating conditions.
The EMIF is used to interface with external memory devices such as DDR2, DDR3, and asynchronous SRAM. The EMIF is configured using the EMIF controller registers, and the memory timing parameters are set using the EMIF timing registers.
The ARM core is used for general-purpose processing and running the operating system, while the DSP core is used for digital signal processing tasks such as video and image processing.
TMS320DM365ZCE27 datasheet
by Texas Instruments
