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    Part Img SST29EE020-120-4C-PH datasheet by Silicon Storage Technology

    • 2 Mbit (256K x 8) page-mode EEPROM
    • Original
    • No
    • Unknown
    • Obsolete
    • EAR99
    • 8542.32.00.51
    • 8542.32.00.50
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    SST29EE020-120-4C-PH datasheet preview

    SST29EE020-120-4C-PH Frequently Asked Questions (FAQs)

    • The SST29EE020-120-4C-PH has a minimum of 100,000 erase cycles per sector, and a minimum of 10,000 erase cycles per block.
    • The HOLD# pin should be driven low to pause the current operation, and driven high to resume the operation. It's recommended to use the HOLD# pin to pause the operation during power-down or power-up sequences.
    • The recommended power-up sequence is to apply VCC first, followed by VPP (if used), and then the clock signal. The device should be in a standby mode during power-up.
    • The device's status can be determined by monitoring the RY/BY# pin, which goes low during a write or erase operation and returns high when the operation is complete.
    • The WP# pin is a write protect pin that prevents writing to the status register. To use it, drive WP# low to enable write protection, and drive WP# high to disable write protection.
    Supplyframe Tracking Pixel