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    Part Img SN74LS76ADR datasheet by Texas Instruments

    • Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-SOIC 0 to 70
    • Original
    • No
    • No
    • Obsolete
    • 8542.39.00.01
    • 8542.39.00.00
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    SN74LS76ADR datasheet preview

    SN74LS76ADR Frequently Asked Questions (FAQs)

    • The maximum clock frequency of the SN74LS76ADR is 25 MHz.
    • The SN74LS76ADR requires a single 5V power supply, and it's recommended to use a decoupling capacitor of 0.1uF to 1uF between VCC and GND to ensure proper power supply decoupling.
    • The SN74LS76ADR can sink or source up to 24mA of current per output pin.
    • The CLR input should be tied to VCC through a pull-up resistor (e.g., 1kΩ) to ensure that the flip-flops are properly reset. A low-going pulse on CLR will reset the flip-flops.
    • The typical propagation delay of the SN74LS76ADR is 10ns to 15ns, depending on the operating conditions and load capacitance.
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