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    Part Img SN74LS373N datasheet by Texas Instruments

    • OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
    • Original
    • Yes
    • Yes
    • Active
    • EAR99
    • 8542.39.00.01
    • 8542.39.00.00
    • Find it at Findchips.com

    SN74LS373N datasheet preview

    SN74LS373N Frequently Asked Questions (FAQs)

    • The maximum clock frequency of the SN74LS373N is 20 MHz, but it can vary depending on the specific application and operating conditions.
    • To ensure proper power and decoupling, use a 5V power supply, add a 0.1uF ceramic capacitor between VCC and GND, and use a 10uF electrolytic capacitor between VCC and GND for bulk decoupling.
    • The SN74LS373N can sink up to 24mA and source up to 12mA per output, but it's recommended to limit the current to 10mA per output to ensure reliable operation.
    • The CLR input should be tied to VCC through a 1kΩ resistor to prevent accidental clearing of the registers. When CLR is low, the registers are cleared, and when CLR is high, the registers are enabled.
    • The propagation delay of the SN74LS373N is typically around 10-15ns, but it can vary depending on the specific application and operating conditions.
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