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    Part Img SN74109N datasheet by Texas Instruments

    • SN74109 - Dual J-/K Positive-Edge-Triggered Flip-Flops with Clear and Preset 16-PDIP 0 to 70
    • Original
    • No
    • No
    • Obsolete
    • 8542.39.00.01
    • 8542.39.00.00
    • Find it at Findchips.com

    SN74109N datasheet preview

    SN74109N Frequently Asked Questions (FAQs)

    • The maximum clock frequency of the SN74109N is 10 MHz, but it can operate at higher frequencies with reduced voltage and/or lower temperatures.
    • To ensure proper power sequencing, apply power to the VCC pin before applying a clock signal to the CLK pin. Also, ensure that the VCC pin is stable before applying any input signals.
    • The recommended operating voltage range for the SN74109N is 4.5V to 5.5V, with a typical operating voltage of 5V.
    • The RST input is active-low, meaning it should be pulled low to reset the device. When RST is low, all outputs are reset to a low state. When RST returns high, the device resumes normal operation.
    • The MR input is used to reset the internal counters and flip-flops of the device. When MR is low, the device is reset, and all counters and flip-flops are cleared.
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