SN65LVDS86AQDGG datasheet by Texas Instruments

SN65LVDS86AQDGG Frequently Asked Questions (FAQs)

• What is the maximum cable length that can be used with the SN65LVDS86AQDGG?
  The maximum cable length depends on the specific application and the signal frequency. As a general rule, the maximum cable length for LVDS signals is around 10-15 meters. However, it's recommended to consult the TI application note 'LVDS Owner's Manual' (SLWC073) for more detailed information on cable length and signal integrity.
• How do I terminate the LVDS lines in my design?
  The SN65LVDS86AQDGG has internal 100-ohm differential termination resistors, so no external termination resistors are required. However, it's recommended to add a 0.1-uF to 1-uF capacitor between the VCC and GND pins to filter the power supply and reduce noise.
• What is the maximum data rate that the SN65LVDS86AQDGG can support?
  The SN65LVDS86AQDGG can support data rates up to 1.92 Gbps. However, the actual data rate may be limited by the specific application, PCB layout, and signal integrity.
• Can I use the SN65LVDS86AQDGG in a multi-point LVDS bus?
  No, the SN65LVDS86AQDGG is designed for point-to-point LVDS connections only. It's not suitable for multi-point LVDS buses, as it does not have the necessary bus-termination resistors or bus- arbitration logic.
• How do I handle skew and jitter in my LVDS design?
  Skew and jitter can be handled by using a clock signal that is transmitted along with the data signals, and by using a PLL or clock-data recovery circuit to re-clock the data signals at the receiver end. Additionally, it's recommended to use a well-designed PCB layout with matched trace lengths and impedance control to minimize skew and jitter.