A good PCB layout is crucial for the PT4562N. TI recommends a 4-layer board with a solid ground plane, and to keep the input and output traces separate to minimize noise coupling. Additionally, place the input capacitors close to the IC and use a low-ESR capacitor for the output filter.
To ensure stability, make sure to follow the recommended component values and PCB layout. Also, add a 10nF capacitor between the VCC pin and GND to filter out high-frequency noise. If oscillations occur, try adding a 1kΩ resistor in series with the output capacitor or increasing the output capacitor value.
Although the datasheet specifies a maximum input voltage of 42V, it's recommended to limit the input voltage to 40V to ensure reliable operation and prevent damage to the IC.
The output voltage ripple and noise can be calculated using the formula: ΔVout = (Iout * Rcoil) / (Lcoil * fsw), where Iout is the output current, Rcoil is the coil resistance, Lcoil is the coil inductance, and fsw is the switching frequency. You can also use TI's WEBENCH tool to simulate and estimate the output voltage ripple and noise.
A low-ESR ceramic capacitor (e.g., X5R or X7R) with a value between 10μF to 22μF is recommended for the input capacitor. This helps to filter out high-frequency noise and ensure stable operation.
PT4562N datasheet
by Texas Instruments
