PLL1706DBQ datasheet by Texas Instruments

PLL1706DBQ Frequently Asked Questions (FAQs)

• What is the recommended PCB layout for PLL1706DBQ to minimize noise and ensure optimal performance?
  Texas Instruments recommends a 4-layer PCB with a solid ground plane, and to keep the PLL circuitry away from noisy components. Additionally, use short traces, and avoid vias and right-angle bends in the signal paths.
• How do I choose the correct values for the loop filter components (R1, R2, C1, C2) in the PLL1706DBQ?
  Use the PLL1706DBQ calculator tool or consult the application note (SLVA466) to determine the optimal values for the loop filter components based on the desired frequency range, phase noise, and loop bandwidth.
• What is the maximum input frequency that the PLL1706DBQ can handle?
  The PLL1706DBQ can handle input frequencies up to 1.6 GHz, but the maximum frequency is dependent on the specific application and the quality of the input signal.
• How do I ensure that the PLL1706DBQ is properly powered and decoupled?
  Use a low-noise power supply, and decouple the PLL1706DBQ with a 10nF capacitor between VCC and GND, and a 100nF capacitor between VCCA and GND. Additionally, use a separate power plane for the PLL circuitry.
• What is the typical lock time for the PLL1706DBQ, and how can I optimize it?
  The typical lock time for the PLL1706DBQ is around 1-2 ms, but it can be optimized by adjusting the loop filter components, using a faster lock detect circuit, and ensuring a clean and stable input signal.