Texas Instruments recommends a 4-layer PCB with a solid ground plane, and to keep the PLL circuitry away from high-frequency signals and noise sources. Additionally, use short and wide traces for the power supply and ground connections, and avoid vias under the device.
Use the PLL1705DBQR Loop Filter Calculator tool provided by Texas Instruments to determine the optimal values for your specific application. The tool takes into account the desired loop bandwidth, phase margin, and other parameters to provide recommended component values.
The PLL1705DBQR can handle input frequencies up to 350 MHz. However, the maximum input frequency may be limited by the specific application and the quality of the input signal.
Use a low-ESR capacitor (e.g., 0.1 μF) connected between the VCC pin and the GND pin, and a 10 μF capacitor connected between the VCC pin and the GND pin for decoupling. Additionally, ensure that the power supply is clean and well-regulated, and that the device is operated within the recommended voltage range (2.97 V to 3.63 V).
The typical lock time for the PLL1705DBQR is around 1 ms to 2 ms. To optimize the lock time, ensure that the input signal is clean and stable, and that the loop filter components are properly selected. Additionally, consider using a faster lock time mode (e.g., Fast Lock mode) if available, and optimize the PLL settings for your specific application.
PLL1705DBQR datasheet
by Texas Instruments
