The recommended power-up sequence is to apply VCC first, followed by VDD, and then the clock signal. This ensures proper initialization of the device.
To optimize THD+N performance, ensure that the input signal is properly terminated, use a low-noise power supply, and optimize the clock frequency and jitter. Additionally, use the internal PLL to generate the clock signal, and adjust the gain settings to minimize distortion.
The maximum input signal level that the PCM5310PAPR can handle is 2.5Vrms. Exceeding this level may result in distortion and decreased performance.
To configure the PCM5310PAPR for master clock mode, set the MCLK pin to the desired clock frequency, and set the BCK pin to the desired bit clock frequency. Then, set the WS pin to the desired word select frequency, and configure the serial data format using the SDIN pin.
The PLL loop filter components (R1, R2, C1, and C2) are used to filter the PLL clock signal and reduce jitter. They help to improve the overall clock signal quality and ensure stable operation of the device.
PCM5310PAPR datasheet
by Texas Instruments
