The recommended power-up sequence is to apply VCC first, followed by VDD, and then the clock signal. This ensures that the internal voltage regulators are powered up correctly and the device is properly initialized.
To configure the PCM5101PW for master clock mode, set the MCLK pin to the desired clock frequency (e.g. 256fs or 512fs) and set the BCK pin to the bit clock frequency (e.g. 64fs or 128fs). Then, set the WS pin to the word select frequency (e.g. fs). Finally, set the SDOUT pin to the desired audio data format (e.g. I2S or DSP).
The maximum output voltage swing of the PCM5101PW is 2.1Vpp differential, which is equivalent to 1.05Vpp single-ended. This is specified in the datasheet as the maximum output voltage swing for the analog output stage.
To reduce EMI emissions from the PCM5101PW, use a solid ground plane, keep the analog and digital signal traces separate, and use shielding or filtering on the output signals. Additionally, ensure that the device is properly decoupled and that the power supply is clean and well-regulated.
The recommended layout and routing for the PCM5101PW involves keeping the analog and digital signal traces separate, using a solid ground plane, and minimizing the length of the clock and data signal traces. Additionally, ensure that the device is placed close to the analog output stage and that the power supply decoupling capacitors are placed close to the device.
PCM5101PW datasheet
by Texas Instruments
