The recommended power-up sequence is to apply VDD first, followed by VDDA, and then the clock signal. This ensures proper initialization of the device.
The analog input filter should be designed to reject noise and aliasing. A 3rd-order Butterworth filter with a cutoff frequency of 10 kHz to 20 kHz is recommended. The filter should also provide a gain of 0 dB to 6 dB to optimize the signal-to-noise ratio.
The maximum clock frequency is 128 fs (fs = sampling frequency). However, it's recommended to use a clock frequency of 64 fs or lower to ensure proper operation and to minimize jitter sensitivity.
The PCM4220PFB outputs 24-bit data in a 2's complement format. The data should be processed in a 24-bit or 32-bit processor or DSP to maintain the full dynamic range. The data can be processed in a signed integer format or converted to a floating-point format for further processing.
The PCB layout should ensure that the analog and digital signals are separated and shielded from each other. The analog input traces should be short and direct, and the digital output traces should be routed away from the analog inputs. A solid ground plane and decoupling capacitors are also recommended.
PCM4220PFB datasheet
by Texas Instruments
