The recommended power-up sequence is to apply VDD first, followed by VCC, and then the clock signal. This ensures proper initialization of the device.
To minimize noise and EMI, it is recommended to keep the analog and digital signal traces separate, use a solid ground plane, and place decoupling capacitors close to the device. Additionally, use a shielded cable for the audio input and output signals.
The maximum clock frequency that can be used with the PCM3500EG4 is 50 MHz. However, it is recommended to use a clock frequency of 24.576 MHz or 22.5792 MHz for optimal performance.
The PCM3500EG4 can be configured for 24-bit or 32-bit audio data by setting the appropriate values for the DBF (Data Bit Format) and WLF (Word Length Format) registers. Refer to the datasheet for the specific register settings for each configuration.
The recommended termination scheme for the PCM3500EG4's digital output is to use a 50-ohm termination resistor to match the impedance of the transmission line. This ensures proper signal integrity and minimizes reflections.
PCM3500EG4 datasheet
by Texas Instruments
