The recommended power-up sequence is to apply VCC first, followed by AVCC, and then the analog input signals. This ensures proper internal biasing and prevents damage to the device.
To optimize the analog input impedance, use a series resistor (Rs) and a shunt capacitor (Cs) to match the impedance of the input signal. The recommended values are Rs = 1 kΩ and Cs = 10 nF.
The maximum clock frequency for the PCM3006T/2K is 256 fs (fs = 44.1 kHz, 48 kHz, or 96 kHz). Exceeding this frequency may result in incorrect data conversion.
The PCM3006T/2K outputs data in a 24-bit, MSB-first, two's complement format. Ensure that your receiving device is configured to accept this format to avoid data corruption.
To minimize noise and ensure proper operation, keep analog and digital signals separate, use a solid ground plane, and route analog signals away from digital signals. Also, use a decoupling capacitor (e.g., 10 μF) between VCC and GND.