The recommended power-up sequence is to apply VCC first, followed by VDD, and then the analog power supplies (VAA and VBB). This ensures that the internal voltage regulators are powered up correctly.
To optimize performance, ensure that the analog power supplies (VAA and VBB) are well-filtered and decoupled, and that the digital power supply (VDD) is separated from the analog power supplies. Additionally, use a low-noise clock source and ensure that the clock signal is properly terminated.
The maximum clock frequency is 256 fs (384 kHz), but it's recommended to use a clock frequency of 128 fs (192 kHz) or lower to ensure optimal performance and minimize jitter sensitivity.
The PCM3002EG/2K can be configured for master or slave mode by setting the M/S pin high or low, respectively. In master mode, the device generates the clock signal, while in slave mode, it receives the clock signal from an external source.
The recommended layout and routing involves separating the analog and digital signals, using a star-ground configuration, and minimizing the length of the clock signal traces. Additionally, ensure that the power supply traces are wide and well-decoupled.
PCM3002EG/2K datasheet
by Texas Instruments
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