PCM2900BDB datasheet by Texas Instruments

PCM2900BDB Frequently Asked Questions (FAQs)

• What is the recommended power-up sequence for the PCM2900BDB?
  The recommended power-up sequence is to apply VCC first, followed by VDD, and then the analog power supplies (VAA and VCCO). This ensures that the internal voltage regulators are powered up correctly.
• How do I configure the PCM2900BDB for master mode operation?
  To configure the PCM2900BDB for master mode operation, set the M/S pin high and ensure that the BCK pin is driven by the PCM2900BDB. The device will then generate the clock signals for the audio interface.
• What is the maximum clock frequency supported by the PCM2900BDB?
  The maximum clock frequency supported by the PCM2900BDB is 50 MHz. However, the recommended clock frequency is 12.288 MHz for 44.1 kHz audio sampling rate and 24.576 MHz for 48 kHz audio sampling rate.
• How do I implement a FIFO buffer in the PCM2900BDB?
  The PCM2900BDB has a built-in FIFO buffer that can be enabled by setting the FIFOEN bit in the control register. The FIFO buffer is 256 words deep and can be used to buffer audio data during transmission or reception.
• What is the purpose of the VREF pin on the PCM2900BDB?
  The VREF pin is used as a reference voltage for the analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) in the PCM2900BDB. It should be connected to a stable voltage source, typically 2.5V or 3.3V, depending on the application.