The recommended power-up sequence is to apply VCC first, followed by AVCC, and then the analog input signals. This ensures proper internal biasing and prevents any potential latch-up conditions.
To minimize noise and EMI, it is recommended to keep the analog and digital grounds separate, use a solid ground plane, and keep the analog input traces as short as possible. Additionally, use a ferrite bead or a 10-ohm resistor in series with the VCC pin to filter out high-frequency noise.
The maximum allowed input voltage for the PCM1851APJT is 2.5Vrms, which is the maximum analog input voltage that can be applied to the device without causing damage or distortion.
To configure the PCM1851APJT for master mode operation, connect the MCLK pin to an external clock source, and set the BCLK pin to the desired bit clock frequency. Additionally, set the WS pin to the desired word select frequency, and configure the serial data interface pins (SDI and SDO) accordingly.
The typical latency of the PCM1851APJT is around 12-15 clock cycles, depending on the specific configuration and operating mode. This latency is due to the internal processing and filtering of the analog-to-digital conversion process.
PCM1851APJT datasheet
by Texas Instruments
