The recommended power-on sequence is to apply VCC first, followed by VREF, and then the analog input signals. This ensures proper device operation and prevents damage to the device.
To optimize the analog input stage, use a low-pass filter to remove high-frequency noise, and ensure the input signal is within the recommended common-mode voltage range (VCM). Also, use a high-impedance source and a low-capacitance cable to minimize signal attenuation.
The recommended clock frequency for the PCM1804DBR is between 256 fs and 512 fs, where fs is the sampling frequency. This ensures proper device operation and minimizes jitter.
The PCM1804DBR outputs 24-bit data in MSB-first format. Ensure that your receiving device can handle this format and that you are using the correct data alignment and byte ordering.
The maximum allowed input signal amplitude for the PCM1804DBR is 2.5 Vpp differential. Exceeding this amplitude may result in distortion and decreased performance.