The recommended power-up sequence is to apply VCC first, followed by VREF, and then the clock signal. This ensures that the internal voltage regulators and analog circuits are properly initialized.
To optimize the analog input circuitry, use a low-pass filter with a cutoff frequency below 20 kHz to remove high-frequency noise, and ensure that the input signal is within the recommended common-mode voltage range (VCC/2 ± 1V). Additionally, use a high-quality, low-noise analog power supply and keep the analog input traces away from digital signals.
The maximum clock frequency that can be used with the PCM1804 is 256 fs (where fs is the sampling frequency). For example, for a sampling frequency of 44.1 kHz, the maximum clock frequency would be 11.2896 MHz.
To minimize the impact of clock jitter, use a high-quality clock source with low jitter (< 100 ps) and ensure that the clock signal is properly terminated and decoupled. Additionally, use a clock frequency that is a multiple of the sampling frequency to reduce jitter-induced errors.
To ensure optimal performance, follow these layout and routing guidelines: keep analog and digital signals separate, use a solid ground plane, and route the analog input signals away from digital signals. Additionally, use a low-impedance power supply and decouple the power pins with high-quality capacitors.
PCM1804DBG4 datasheet
by Texas Instruments
