The recommended power-on sequence is to apply VCC first, followed by VREF, and then the analog input signals. This ensures proper device operation and prevents damage.
To optimize the analog input stage, use a low-pass filter to remove high-frequency noise, and ensure the input signal is within the recommended range of 0.5V to 2.5V. Also, use a high-impedance source and a low-capacitance cable to minimize signal degradation.
The recommended clock frequency for the PCM1802DBR is between 2.4 MHz and 50 MHz. However, the optimal clock frequency depends on the specific application and sampling rate requirements.
To minimize clock jitter and phase noise, use a high-quality clock source, such as a crystal oscillator, and ensure the clock signal is clean and stable. You can also use a clock jitter attenuator or a phase-locked loop (PLL) to further reduce jitter and phase noise.
The maximum allowed input voltage for the PCM1802DBR is 3.6V. Exceeding this voltage can damage the device.
PCM1802DBR datasheet
by Texas Instruments
