The recommended power-on sequence is to apply VCC first, followed by VREF, and then the analog input signals. This ensures proper device operation and prevents damage to the internal circuitry.
To optimize the analog input stage, use a low-pass filter to remove high-frequency noise, and ensure the input signal is within the recommended common-mode voltage range (VCM). Additionally, use a high-impedance source and a low-capacitance layout to minimize signal attenuation.
The recommended clock frequency for the PCM1801U/2K is between 2.048 MHz and 12.288 MHz. However, the device can operate with clock frequencies up to 25 MHz, but with reduced performance.
The PCM1801U/2K outputs 24-bit data in a MSB-first, left-justified format. Ensure that your receiving device can handle this format, and consider using a FIFO or buffer to handle the data stream.
The VREF pin is the reference voltage input for the analog-to-digital converter. Connect a 2.5V reference voltage source to the VREF pin, and ensure it is decoupled with a 10uF capacitor to ground.