The recommended power-up sequence is to apply VCC first, followed by VCCO, and then the digital inputs. This ensures that the internal voltage regulators are powered up correctly and prevents any potential latch-up conditions.
To minimize noise and jitter, it is recommended to keep the analog and digital signal traces separate, use a solid ground plane, and place the device close to the analog power supply. Additionally, use a low-ESR capacitor for the VCCO pin and a 10uF capacitor for the VCC pin.
The PCM1792DB can support clock frequencies up to 256fs, where fs is the sampling frequency. For example, for a 192kHz sampling frequency, the maximum clock frequency would be 49.152MHz.
To configure the PCM1792DB for Master Clock mode, set the MCLK pin to the desired clock frequency, and set the BCK pin to the bit clock frequency (typically 64fs). The device will then generate the LRCK signal internally.
The recommended termination for the digital output pins is a 50-ohm resistor to ground, to match the impedance of the output drivers and prevent signal reflections.
PCM1792DB datasheet
by Texas Instruments
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