The recommended power-up sequence is to apply VCC first, followed by VDD, and then the digital power supply (VCCIO). This ensures that the internal voltage regulators are powered up correctly.
To configure the PCM1772RGA for master clock mode, set the MCLK pin to the desired clock frequency (e.g., 256fs or 512fs) and set the BCK pin to the desired bit clock frequency (e.g., 64fs or 128fs). Then, set the WS pin to the desired word clock frequency (e.g., fs or 2fs).
The maximum input voltage for the ADC inputs is VREF (typically 2.5V or 5V), which is the reference voltage for the ADC. Exceeding this voltage may cause damage to the device.
To optimize performance, ensure that the analog power supply (VCC) is well-regulated and decoupled, and that the digital power supply (VCCIO) is also well-regulated and decoupled. Additionally, use a low-noise, high-quality clock source, and ensure that the PCB layout is optimized for noise reduction.
The recommended layout and routing for the PCM1772RGA involves separating the analog and digital power supplies, using a star-ground configuration, and keeping the analog and digital signal traces separate and away from each other. Additionally, use a solid ground plane and avoid vias under the device.
PCM1772RGA datasheet
by Texas Instruments
