The recommended power-up sequence is to apply VCC first, followed by VDD, and then the clock signal. This ensures proper initialization of the device.
To minimize noise and EMI, it is recommended to keep the analog and digital signal traces separate, use a solid ground plane, and place decoupling capacitors close to the device. Additionally, use a shielded cable for the I2S interface and keep it away from other high-frequency signals.
The maximum clock frequency that can be used with the PCM1772PW is 50 MHz. However, it is recommended to use a clock frequency of 12.288 MHz or 24.576 MHz for optimal performance.
To configure the PCM1772PW for Master Clock mode, set the MCLK pin to the desired clock frequency and set the BCK pin to the desired bit clock frequency. Then, set the WS pin to the desired word select frequency and configure the I2S interface accordingly.
The recommended termination scheme for the I2S interface is to use a series resistor (Rs) of 22 ohms to 47 ohms and a parallel capacitor (Cp) of 10 pF to 22 pF at the transmitter end, and a series resistor (Rs) of 22 ohms to 47 ohms at the receiver end.
PCM1772PW datasheet
by Texas Instruments
