The recommended power-up sequence is to apply VCC first, followed by AVCC, and then DVCC. This ensures that the internal voltage regulators are powered up correctly.
To optimize the PCB layout, keep the analog and digital grounds separate, use a solid ground plane, and place the analog components close to the PCM1748KE. Also, use a low-impedance path for the clock signal and keep the clock signal away from the analog signals.
The maximum clock frequency that can be used with the PCM1748KE is 256 fs (where fs is the sampling frequency). However, it's recommended to use a clock frequency that is 10-20 times the sampling frequency to ensure proper operation.
To configure the PCM1748KE for master clock mode, set the MCLK pin to the desired clock frequency, and set the BCK pin to the bit clock frequency (which is typically 64 times the sampling frequency). Also, set the LRCK pin to the word clock frequency (which is typically the sampling frequency).
The recommended termination for the digital output pins is a 50-ohm resistor to ground, which helps to reduce electromagnetic interference (EMI) and improve signal integrity.
PCM1748KE datasheet
by Texas Instruments
