The recommended power-up sequence is to apply VCC first, followed by VDD, and then the digital inputs. This ensures that the internal voltage regulators are powered up correctly and the device is properly initialized.
To minimize noise and EMI, it is recommended to keep the analog and digital signal traces separate, use a solid ground plane, and place decoupling capacitors close to the device. Additionally, use a low-impedance power supply and avoid running digital signals near the analog inputs.
The maximum clock frequency that can be used with the PCM1744U/2K is 192 kHz. However, it is recommended to use a clock frequency of 128 kHz or lower to ensure optimal performance and minimize jitter.
To configure the PCM1744U/2K for master clock mode, set the MCLK pin to the desired clock frequency and set the BCK pin to the desired bit clock frequency. The device will then generate the LRCK signal internally.
The recommended termination scheme for the digital outputs of the PCM1744U/2K is to use a 50-ohm resistor in series with a 50-pF capacitor to ground. This helps to reduce reflections and improve signal integrity.
PCM1744U/2K datasheet
by Texas Instruments
