The recommended power-up sequence is to apply VCC first, followed by VDD, and then the digital inputs. This ensures that the internal voltage regulators are powered up correctly and prevents any potential latch-up conditions.
To minimize noise and EMI, it is recommended to keep the analog and digital signal traces separate, use a solid ground plane, and place decoupling capacitors close to the device. Additionally, use a shielded cable for the analog input signals and keep the PCB layout symmetrical to reduce radiation.
The maximum allowed clock jitter for the PCM1733U is 100 ps peak-to-peak. Exceeding this limit can result in increased distortion and decreased SNR.
To configure the PCM1733U for master clock mode, set the MCLK pin to the desired clock frequency, and set the BCK pin to the desired bit clock frequency. The device will then generate the LRCK signal internally.
The recommended termination scheme for the digital output signals is to use a 50-ohm resistor in series with a 50-ohm load, and to AC-couple the signals to the receiving device. This ensures that the signals are properly terminated and reduces the risk of signal reflections.
PCM1733U datasheet
by Texas Instruments
